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| Various Discrete Power MOSFETs |
In modern electrical and electronic systems, the Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of the most important and widely used semiconductor devices. Its high input impedance, fast switching capability, and low power consumption offer significant advantages over conventional Bipolar Junction Transistors (BJTs), making it the dominant switching device in applications ranging from low-power digital circuits to high-power energy conversion systems. Ever since its introduction in the 1960s, the MOSFET has undergone continuous structural refinement, with power-focused variants emerging from the 1970s onward to meet increasingly demanding requirements for efficiency, power handling capability, and switching speed. The progression from planar MOSFETs to VMOS, DMOS, trench-gate, split/shield-gate, and superjunction technologies reflects a series of engineering solutions aimed at reducing conduction losses while maintaining high breakdown voltages and reliable operation. As these device structures form the foundation of contemporary power electronics, we'll be conducting a technical investigation into their development in order to understand the engineering challenges that drove these innovations and to evaluate how successive structural improvements have enhanced device performance.
The Original Planar MOSFET
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| Cross Section Diagram of a P-Channel MOSFET |
The first silicon MOSFET structure was demonstrated in 1960 by D. Kahng and M. M. Atalla of Bell Labs. Which establishes the fundamental operating principle upon which all subsequent power MOSFET structures are built on. The idea is that an external electric field, typically generated by a voltage applied to the gate, causes band bending (i.e. the shifting of a semiconductor's energy bands due to an applied electric field, causing carriers to accumulate, deplete, or invert in a region of the material) at the surface of an n-type semiconductor. If the band bending is sufficiently strong, the surface enters inversion and becomes rich in holes, forming a p-type inversion layer that modulates the surface conductivity. This describes a p-channel MOSFET, which are also the first commercially available MOSFETs (n-channel ones, the ones the most common today, are developed at the same time, but doesn't work quite as well due to fabrication limitations).
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| Diagram of a MOSFET depicted in Kahng's Patent (Source:https://patentimages.storage.googleapis.com/8c/18/90/4fbadebd183ee7/US3102230.pdf) |
This groundbreaking device was the planar MOSFET, in which the source and drain regions are fabricated on the same side of the silicon wafer, with current flowing laterally through the inversion channel beneath the gate oxide. The stable silicon-oxide interface it relied upon allowed precise photolithographic patterning and became the foundation for all early MOSFETs and integrated circuits. Although this structure laid the essential groundwork for transistor scaling and integration, it had significant limitations for power applications: with current flowing laterally along the surface, the device required a large silicon area to achieve higher current-handling capability, resulting in higher on-resistance and poor utilisation of the available wafer area. To overcome these drawbacks, engineers began developing vertical MOSFET architectures in the early 1970s that allowed current to flow perpendicular to the wafer surface, with one of the first successful approaches being the VMOS, or V-groove MOSFET, which we'll look at in the next section.
V-Groove MOSFET (VMOS)
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| Cross Section of a P-Channel VMOS MOSFET |
The V-groove MOSFET, or VMOS, emerged in the early 1970s and represented the first successful attempt to orient current flow vertically through the silicon. Developed by F. E. Holmes and C. A. T. Salama, the technology utilised anisotropic etching (i.e. a directional etching process that removes silicon at significantly different rates depending on the crystal plane orientation, enabling precise, sharp features with vertical or sloped sidewalls) of silicon to create a V-shaped groove in the semiconductor surface, allowing the transistor channel to be formed along the sloped sidewalls of the groove rather than across a flat planar surface. This approach enabled significantly shorter channel lengths while maintaining relatively relaxed lithographic alignment requirements.
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| Siliconix VN66AF MOSFET, constructed with the VMOS structure |
The operating principle remains fundamentally the same as that of a conventional MOSFET. When a sufficient gate voltage is applied, an electric field penetrates through the gate oxide and causes band bending at the semiconductor surface. This attracts charge carriers to the sidewalls of the V-groove, forming an inversion layer that connects the source and drain regions. Current then flows through the channel under the influence of the drain-source voltage. The V-shaped geometry effectively increases the channel width while maintaining a compact device footprint. One of the most significant advantages of VMOS was its ability to achieve short-channel operation without the severe alignment tolerances required by planar MOSFETs. The structure also exhibited reduced gate overlap capacitance because much of the source and drain regions remained covered by thick field oxide. As a result, VMOS devices offered higher transconductance, lower parasitic capacitance, and improved high-frequency performance. Experimental devices reported in the original paper achieved channel lengths as small as 2.3μm, width of 70μm, transconductance values approaching 950μS at VDS = -25V, and breakdown voltage of 35V. Quite revolutionary at the time.
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| VMOS FETs are widely used in Radio Frequency Circuits (Source: https://www.worldradiohistory.com/UK/Bernards-And-Babani/Babani/83-Penfold-VMOS%20projects.pdf) |
Despite these advantages, VMOS had notable drawbacks. The sharp geometry at the bottom of the V-groove concentrated electric fields, increasing the risk of oxide stress and long-term reliability issues. Fabrication complexity was also higher than that of standard planar processes, requiring precise anisotropic etching and careful control of oxide growth within the groove. These limitations motivated the development of an alternative vertical architecture that retained the benefits of vertical current flow while eliminating the problematic V-groove geometry entirely, leading directly to the Double-Diffused MOSFET, or DMOS, which we'll be discussing in the next section.
Double-Diffused MOSFET (DMOS)
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| Cross section of a typical Vertical DMOS FET (Source: https://www.researchgate.net/figure/Schematic-cross-section-of-a-typical-Vertical-DMOS-VDMOS-transistor_fig8_50319290) |
The double-diffused MOSFET, or DMOS, resolved many of the limitations of VMOS by eliminating the V-groove entirely. Instead of relying on a physical trench to define the channel, DMOS forms the channel using two successive thermal diffusion processes: a p-type body diffusion followed by an n+ source diffusion (hence double diffused). Since the p-type diffusion penetrates laterally further than the shallower n+ source diffusion, the channel length is defined by the difference in their lateral diffusion depths rather than by photolithographic dimensions. This self-aligned double-diffusion technique enabled channel lengths of less than 1μm to be achieved without requiring sub-micron lithography, representing a significant manufacturing advantage over conventional planar MOSFET fabrication.
Unlike VMOS, DMOS gets rid of the sharp V-shaped groove that concentrated electric fields at the groove apex, improving oxide reliability and simplifying fabrication process. As anisotropic etching is no longer used, this made the manufacturing process more compatible with conventional planar processing techniques, resulting in higher production yields and improved device consistency. Furthermore, the use of a lightly doped drift region (i.e. a lightly doped epitaxial layer located between the channel/body and the heavily doped drain, designed to support high blocking voltages by absorbing the depletion region while keeping on-state resistance as low as possible.) enabled the depletion region to extend primarily into the drift layer rather than the channel, allowing the breakdown voltage and channel length to be designed virtually independently. Therefore, DMOS devices could achieve high breakdown voltages, low on-state resistance, and high transconductance, making them well suited for high-power and high-frequency switching applications.
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| IRF540N MOSFET, a popular MOSFET with the VDMOS structure |
Compared with both planar MOSFETs and VMOS devices, DMOS offered a more practical balance between manufacturability, reliability and electrical performance. The structure retained the advantages of a vertical device (hence sometimes referred to as VDMOS) while eliminating the reliability concerns associated with V-groove designs, ultimately establishing DMOS as the dominant foundation for modern power MOSFET technologies, with devices such as the widely used IRF540 and its variants being well-known examples. A lateral variant, LDMOS (Lateral DMOS), uses the same double-diffusion channel principle but routes current horizontally across the wafer surface rather than vertically through the substrate. Where VDMOS is optimised for discrete power switching, benefiting from the low on-resistance that a vertical current path and thick drift region provide, LDMOS trades some of that conduction efficiency for superior integration with planar IC processes and excellent high-frequency characteristics, making it the preferred choice in modern RF circuitry. Although current flows laterally as in the original planar MOSFET, LDMOS differs fundamentally in that the planar structure lacks the dedicated drift region and double-diffusion channel needed to sustain high blocking voltages at useful current densities. One limitation that VDMOS variants share, however, is the parasitic JFET region that forms between adjacent p-body diffusions, which increasingly restricts performance as cell density is pushed higher. Subsequent developments, including trench-gate MOSFETs, would build directly upon the vertical DMOS concept to address this constraint and achieve even higher cell densities and lower on-resistance, as we will see in the next section.
Trench-Gate MOSFET
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| Cross Section Diagram of a Trench-Gate VDMOS FET (Source: https://ieeexplore.ieee.org/document/7862948?figureId=fig2#fig2) |
Although DMOS significantly improved upon the earlier VMOS structure, its performance remained constrained by the parasitic JFET region between adjacent p-body diffusions, where the depletion regions spreading from each p-body pinch the current path through the drift region. As cell density increased to reduce on-state resistance, this narrowing conduction path introduced additional resistance and limited further performance improvements, establishing a clear ceiling on how far planar DMOS scaling could be pushed. The trench-gate MOSFET addressed these limitations by replacing the planar gate with a gate electrode formed inside deep vertical trenches etched into the silicon. Rather than forming the inversion channel across the wafer surface as in planar DMOS, the channel is created along the vertical sidewalls of each trench when a positive gate voltage is applied, eliminating the JFET region entirely by allowing the trenches to extend through the p-body and into the drift region below. This vertical configuration enables a much higher packing density of individual cells, lower channel resistance, and a significant reduction in overall on-resistance.
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| Infineon IPP023N03LF2S MOSFET with the Trench-Gate structure |
As semiconductor fabrication technology advanced, trench-gate MOSFETs rapidly evolved through continual reductions in size. Improvements such as self-aligned processing, high-energy ion implantation, and finer lithographic techniques enabled increasingly smaller cell dimensions and unprecedented cell densities. These manufacturing advances produced devices with substantially lower specific on-resistance than earlier planar MOSFETs, allowing compact packages to achieve performance previously attainable only with much larger devices. However, as cell density continued to increase, further reductions in on-resistance became progressively limited by parasitic resistances associated with the substrate, package, and interconnections rather than the transistor cells themselves.
While the trench structure greatly improved conduction performance, the close proximity of the gate electrode to the drain region increased the gate-to-drain capacitance, resulting in higher gate charge and greater switching losses. This parasitic capacitance slows switching speed through the Miller effect and increases the energy required to drive the gate at high frequencies. Therefore, later generations of trench MOSFETs focused not only on reducing on-state resistance but also on engineering the electric field and gate structure to minimise parasitic capacitances while maintaining high breakdown voltage and device reliability. Techniques such as thick bottom oxide (TBOX, i.e. a thicker oxide layer deposited specifically at the bottom of the trench gate, increasing the physical separation between the gate electrode and the drain region to directly reduce gate-to-drain capacitance without affecting the thinner sidewall oxide that controls the channel), field-plate structures (i.e. A conductive plate connected to either the gate or source potential that extends into the drift region, reshaping the electric field distribution to spread the voltage more evenly and reduce the peak field concentration, which allows a shorter or more lightly doped drift region for a given breakdown voltage and thereby lowers on-resistance), shielded or split-gate structures, and superjunction architectures were subsequently introduced to address these limitations. We'll be looking at split/shield gate and superjunction architectures in more detail, as those are the most common today.
Split/Shield-Gate MOSFET
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| Cross Section of a Conventional Shield Gate MOSFET, FP refers to the Field Plate (Source: https://figures.semanticscholar.org/86d3c3ff95d0d2e79b79f71545725d006bec491d/1-Figure1-1.png) |
The split-gate, or shield-gate architecture were developed specifically to relieve the electric field stress on the gate oxide at the trench bottom that limited conventional trench-gate devices. In a shield-gate design, the lower portion of the trench is filled with a separate, source-connected polysilicon electrode insulated from the semiconductor by a thicker oxide, while the active gate occupies only the upper portion of the trench. The two terms are often used interchangeably in industry, with split-gate sometimes used to describe the same arrangement more generically. This shielding electrode redistributes the electric field in the drift region, protecting the thinner gate oxide above from peak field concentrations, and because the gate no longer overlaps the full depth of the drift region, gate-to-drain capacitance is substantially reduced compared to conventional trench devices. The result is a significant improvement in the figure of merit relating on-resistance to gate charge, making shield-gate devices particularly attractive for high-frequency power conversion applications such as synchronous rectification in DC-DC converters, and devices based on this principle were commercialised from the early 2000s onward, becoming standard in low-voltage, high-current applications.
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| Toshiba TK7R0E08QM MOSFET with a trench field-plate structure (the same as shield gate) |
Despite these advantages, shield-gate architectures have their own complexities. The additional polysilicon electrode adds process steps and increases fabrication difficulty, and the source-connected shield electrode introduces a parasitic capacitance between the shield and the gate, which partially cancels out some of the switching improvements. The structure also becomes increasingly difficult to optimise as voltage ratings rise, since the thicker bottom oxide and the geometry of the drift region must be carefully balanced to maintain both breakdown voltage and low on-resistance. These constraints mean that while shield-gate devices shine in low to medium voltage applications, typically below around 100 to 200 V, they offer diminishing returns at higher voltages where the drift region must be substantially thicker to support the larger electric field. It is precisely this high-voltage limitation that motivated the development of superjunction architectures, which take a fundamentally different approach to overcoming the relationship between breakdown voltage and on-resistance.
Superjunction MOSFET
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| Cross section diagram of a superjunction MOSFET (Source:https://www.st.com/content/dam/aboutus/innovation-technology/superjunction-mdmesh/pictures/planar-superjunction-602x365.png) |
As mentioned before, while shield-gate and trench architectures addressed many of the limitations of planar DMOS, they did not fundamentally resolve a deeper constraint of all conventional power MOSFETs: the trade-off between breakdown voltage and on-resistance imposed by the silicon material itself. In a conventional vertical device, increasing the breakdown voltage requires a thicker and more lightly doped drift region, which directly increases on-resistance. This relationship, sometimes called the silicon limit, meant that higher-voltage devices inevitably carried a significant conduction penalty regardless of how well the gate structure was optimised.
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| ST STB25N018M9 MOSFET with Superjunction structure |
Superjunction overcomes this limitation by replacing the conventional lightly doped n-type drift region with a special arrangement of alternating, heavily doped p-type and n-type vertical columns. When the device is reverse biased, these columns deplete laterally into one another rather than requiring the vertical thickness of a lightly doped region to sustain the electric field. Because the depletion occurs laterally between the opposing columns, the n-type columns can be doped far more heavily than in a conventional drift region for the same target breakdown voltage. In the on-state, current flows through these heavily doped n-type columns with much lower resistance than a conventional drift region, while in the off-state, the mutual depletion of the column pairs maintains high breakdown voltage. The theoretical basis for this behaviour was described by T. Fujihira in 1997, who derived analytical expressions showing that the specific on-resistance of superjunction devices could be reduced to less than one hundredth of that achievable with conventional devices at equivalent breakdown voltages, with the improvement becoming increasingly pronounced at higher voltages. Infineon commercialised the concept shortly after under the CoolMOS name, and superjunction devices rapidly became the dominant architecture for high-voltage power MOSFETs, particularly in the 500 V to 900 V range used in switched-mode power supplies (SMPS) and motor drivers.
Despite their remarkable performance, superjunction devices still introduce significant drawbacks of their own. The most critical is charge balance: the total charge in each p-type column must be matched very precisely to that of the adjacent n-type column. Any imbalance causes the depletion regions to fail to fully compensate one another, leaving residual charge that concentrates the electric field and substantially reduces breakdown voltage. This sensitivity makes superjunction devices considerably less tolerant of process variation than conventional trench devices, and maintaining acceptable yield requires tight control over epitaxial doping and column geometry across the entire wafer. Fabrication itself is also more demanding, with the columnar structure typically formed either through multiple cycles of epitaxial growth and implantation or through deep trench etching followed by epitaxial refill, both of which add process complexity and cost compared to standard trench MOSFET manufacturing. Additionally, the heavily doped p-columns introduce a significant concentration of stored charge that must be swept out during switching, increasing reverse recovery losses in the body diode and making superjunction devices somewhat more demanding to drive in hard-switching applications compared to an equivalent shield-gate device.
That Brings Us to Today
The progression from the original planar MOSFET through VMOS, DMOS, trench-gate, split/shield-gate, and superjunction architectures represents one of the most sustained and methodical engineering development efforts in the history of semiconductor devices. Each generation addressed a specific limitation of the one before it: VMOS introduced vertical current flow to overcome the area inefficiency of planar devices, DMOS eliminated the reliability concerns of the V-groove while enabling self-aligned short-channel operation, trench-gate devices removed the parasitic JFET bottleneck and dramatically increased cell density, shield-gate structures reduced the gate charge penalty that trench geometries introduced, and superjunction architectures finally broke the silicon material limit that had constrained the relationship between breakdown voltage and on-resistance in all preceding designs.
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| ST SCT1000N170 Silicon Carbide MOSFET |
Today, split/shield-gate and regular trench-gate MOSFETs dominate low to medium voltage applications where gate charge and switching speed are the primary concerns, while superjunction MOSFETs are the standard choice for high-voltage applications in the 500 V to 900 V range. The engineering principles developed across this progression, particularly the concepts of drift region charge management, field plate shaping, and lateral charge compensation, have also carried forward into emerging wide-bandgap semiconductor technologies such as gallium nitride and silicon carbide, where the same fundamental trade-offs between breakdown voltage, on-resistance, and switching performance continue to drive structural innovation. In that sense, the history of power MOSFET development is not simply a record of past solutions, but a strong, inspirational foundation that continues to inform the design of next-generation power transistors.
As always, please feel free to leave a comment and discuss further on this topic. Otherwise, enjoy your week and I'll see you in the next post.
This post draws on the following resources:
- Silicon-Silicon Dioxide Surface Device by D. Kahng (Bell Labs, 1961) in Semiconductor Devices: Pioneering Papers by S. M. Sze (World Scientific, 1991)
- VMOS—A new MOS integrated circuit technology by F. E. Holmes, C.A.T. Salama (Elsevier, 1974)
- Threshold voltage controllability in double-diffused-MOS transistors by M. D. Pocha et. al. (IEEE, 1974)
- An Initial study on The Reliability of Power Semiconductor Devices by B. K. Boksteen et. al. (2010)
- The Trench Power MOSFET: Part I—History, Technology, and Prospects by R. K. Williams et. al. (IEEE, 2017)
- Shield Gate Trench MOSFET With Narrow Gate Architecture and Low-k Dielectric Layer by Z. Wang et. al. (IEEE, 2020)
- Theory of Semiconductor Superjunction Devices by T. Fujihira (Japanese Journal of Applied Physics, 1997)
- RSGB Handbook of Radio Communications 15th Edition by E. Durrant et. al. (Radio Society of Great Britian, 2023)
Acknowledgments:
- The author expresses sincere gratitude to University of Dayton Roesch Library, Ohio, United States for assistance in providing access to Silicon-Silicon Dioxide Surface Device in Semiconductor Devices: Pioneering Papers, and to University of Exeter Forum Library for their persistence in locating and requesting this aforementioned material.
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